SPTS Rapier DRIE
SPTS Rapier DRIE
SPTS Technologies - Omega LPX Rapier
CNS
Harvard University
Center for Nanoscale Systems (CNS)
- Etching
- Dry
- Deep Silicon (Bosch)
Description
The SPTSs Rapier system etches Si using Bosch switched processing for vertical profiles as well as non-switched processing for tapered profiles. The system is equipped with dual plasma sources with independently controlled primary and secondary decoupled plasma zones, with independent dual gas inlets; which results in high etch rate, good uniformity, and less tilting around wafer edge. The Electro-Static Clamping Chuck enables good wafer clamping, less wafer bowing compared with mechanical clamping, and wafer-less chamber cleaning. The attached AMS chiller can control the chuck temperature from -20C to + 40C and the Claritas end point detector can minimize the micro-trenches of SOI wafer etch as well as control the pre-etch and the post-etch cleaning.
Comments
Application Si etch solely High aspect ratio etch: 5 50 Deep etch: 5m through Si wafer etch Broad features: from nano- to mm- scales in lateral dimension Sider wall roughness (scallop depth): 6nm 700nm Only resists and SiO2 or Si3N4 allowed as etching mask Handle samples _ 6 Absolutely no-metal mask or metal stop layer